Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs.In PCS Direct configuration, the data flow is through the PCS block, but all the internal PCS blocks are bypassed.A link is defined as a single entity communication port. A transceiver channel is synonymous with a transceiver lane.For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of 10.3125 Gbps. Each transceiver channel operates at a lane data rate of 10.3125 Gbps.
You can dynamically adjust the PMA parameters, such as differential output voltage swing (Vod), and pre-emphasis settings.
Four transceiver channels give a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B Physical Coding Sublayer (PCS) encoding and decoding).
Each transceiver bank includes four or six transceiver channels in all devices.
The master CGB divides and distributes bonded clocks to a bonded channel group.
It also distributes non-bonded clocks to non-bonded channels across the x6/x N clock network. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.